Paper
Recently, we have successfully developed the novel 3-wafers stacked & 64MP pixel CMOS image sensor (CIS) with 0.5um pixel including through silicon deep contact module and face-to-back Cu-to-Cu hybrid bonding module. In this paper, we demonstrate how to prepare and optimize the 3-wafers stacking processes. First, Bonding void free technology: To attain bonding interface flatness, we modified chemical mechanical polishing (CMP) process and Cu pad pattern density. Second, Cu pad window qualification: Considering thermal expansion and pattern density of Cu pad, various height of Cu pad was evaluated by direct current (DC) test with designed TEG item and adjusted to the best condition. Third, Improvement of through silicon deep contact: To amplify the conversion gain (CG) of 3-wafers stacked CIS, deep contact was totally revised such as critical dimension (CD), height and thickness of sidewall oxide. The CG is highly promoted and noise properties of CIS is also refined. Finally, Bonding distortion: By varying bonding parameter like wafer-to-wafer gap, chuck pressure, and deform method, the distortion of bonded wafer was improved for following lithography and stacking process.