Lanthanide‐doped indium zinc oxide (Ln‐IZO) was employed as the active channel layer (ACT) of thin film transistors (TFTs). The, Ln‐IZO, single‐1 ACT‐based TFT exhibited a high mobility and a small threshold voltage shift (∆VTH) within −1 V after 1‐hour negative bias temperature illumination stress (NBTIS). However, the corresponding ∆ VTH of 1‐hour positive bias temperature stress (PBTS) was as large as over 8 V. Optimized stacked structures of the ACT were adopted and obtained a significantly improved stability of PBTS. TFTs based on double‐2 ACT (Ln‐IZO/IGZO‐1) and triple‐2 ACT (Ln‐IZO/IGZO‐1/IGZO‐2) exhibited significantly lower ∆VTHs of 1.79 and 1.62 V under PBTS, respectively. Meanwhile, the excellent NBTIS stability with ∆VTH within −1 V was maintained for both double‐2‐ and triple‐2‐based TFTs. Furthermore, an appreciated VTH uniformity was obtained for triple‐2‐based TFTs, with a narrow range width of only 0.5 V. At the same time, we proposed a PBTS fitting model, using the stretched power‐law function, ∆ VTH = kTr for the deterioration of Ln‐oxide TFTs under long‐term operation. According to the proposed model, the ∆VTH could be maintained within 6 V even after 200‐hour PBTS for TFT based on triple‐2.

P‐1.9: Enhanced Stability Under Positive Bias Temperature Stress of Ln‐Doped InZnO Thin Film Transistors Fabricated with Back‐channel‐etch Structure