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High-K Gate Dielectric for High-Performance SiC Power MOS... | ResearchHub
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High-K Gate Dielectric for High-Performance SiC Power MOSFET Technology with Low Interface Trap Density, Good Oxide Lifetime (t<sub>tddb</sub>≥ 10<sup>4</sup>s), and High Thermal Stability (≥ 800 °C)
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Authors
Umesh Chand
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Umesh Chand
•
L.K. Bera
10 more
•
Surasit Chung
Published
August 22, 2024
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Journal
Diffusion and defect data, solid state data. Part B, Solid state phenomena/Solid state phenomena
Topics
Physics
Materials Science
Engineering
Electrical And Electronic Engineering
Electronic, Optical And Magnetic Materials
Show all topics
DOI
10.4028/p-a6qptx
License
CC-BY
Supporters
Support the authors with ResearchCoin
Tip RSC
Journal
Diffusion and defect data, solid state data. Part B, Solid state phenomena/Solid state phenomena
Topics
Physics
Materials Science
Engineering
Electrical And Electronic Engineering
Electronic, Optical And Magnetic Materials
Show all topics
DOI
10.4028/p-a6qptx
License
CC-BY