Back Gated Multilayer InSe Transistors with Enhanced Carrier Mobilities via the Suppression of Carrier Scattering from a Dielectric Interface

Abstract

The back gate multilayer InSe FETs exhibit ultrahigh carrier mobilities, surpassing all the reported layer semiconductor based electronics with the same device configuration, which is achieved by the suppression of the carrier scattering from interfacial coulomb impurities or surface polar phonons at the interface of an oxidized dielectric substrate. The room-temperature mobilities of multilayer InSe transistors increase from 64 cm2V−1s−1 to 1055 cm2V−1s−1 using a bilayer dielectric of poly-(methyl methacrylate) (PMMA)/Al2O3. The transistors also have high current on/off ratios of 1 × 108, low standby power dissipation, and robust current saturation in a broad voltage range. As a service to our authors and readers, this journal provides supporting information supplied by the authors. Such materials are peer reviewed and may be re-organized for online delivery, but are not copy-edited or typeset. Technical support issues arising from supporting information (other than missing files) should be addressed to the authors. Please note: The publisher is not responsible for the content or functionality of any supporting information supplied by the authors. Any queries (other than missing content) should be directed to the corresponding author for the article.