Abstract

CdTe devices have reached efficiencies of 22% due to continuing improvements in bulk material properties, including minority carrier lifetime. Device modeling has helped to guide these device improvements by quantifying the impacts of material properties and different device designs on device performance. One of the barriers to truly predictive device modeling is the interdependence of these material properties. For example, interfaces become more critical as bulk properties, particularly, hole density and carrier lifetime, increase. We present device-modeling analyses that describe the effects of recombination at the interfaces and grain boundaries as lifetime and doping of the CdTe layer change. The doping and lifetime should be priorities for maximizing open-circuit voltage (Voc) and efficiency improvements. However, interface and grain boundary recombination become bottlenecks for device performance at increased lifetime and doping levels. This work quantifies and discusses these emerging challenges for next-generation CdTe device efficiency.