The briefing proposes an on-chip system based on the RISC-V instruction set architecture (ISA) for application in accelerator power controllers to address some of the current shortcomings. The processor core adopts a three-stage pipeline design, supports the RV32IM instruction set, and features a custom bus structure. The system is equipped with ROM, RAM, and serial port control modules, along with a debugging module that supports online debugging of the processor core. The implemented instructions have passed the instruction set testing program provided by the RISC-V Foundation. The processor core has been implemented and verified on Xilinx XC7A100T FPGA, with resource requirements of 3134 LUTs and 865 FFs. Additionally, Coremark testing conducted on the processor core yielded a score of 2.44 Coremark/MHz, reaching the level of performance of an ARM Cortex-M0 processor. This meets the performance requirements of the current power controller. The system has been ported to the digital power controller at the Institute of Modern Physics, Chinese Academy of Sciences, achieving successful communication between the controller and host computer. In addition, the core can parse communication protocols.
